|
|
 |
|
|
|
|
Memory Test
System for Mass Production of the High-Speed Devices
such as DDR2-SDRAM and
DDR-SRAM
|
The T5593 lowers
the cost of at-speed test by supporting up to 128
devices simultaneous testing, Hifix exchange only by a
socket board unit, and a new high-throughput calibration
technology. Moreover, yield improvement is realized in
combination with our handlers with Thermal Compensation
Technology. This tester and handler combination is the
optimal mass production solution.
| |
|
|
|
|
128 DUT Simultaneous Testing of
DDR2 -SDRAM
The T5593 memory test system
delivers the highest accuracy at the device socket, even
while simultaneously testing DDR2-SDRAM up to 128
devices. The T5593 has an expanded function of the DQS
Jitter Solution which was included in the T5586 memory
test system. High Speed CLK PINs, which are
indispensable in testing ultra high-speed device testing
(>500MHz), are integrated into the test head.
Simultaneous testing, high-speed and high accuracy
device testing are all delivered for the production
environment.
High Accuracy Device
Interface
New device interfacing was developed
to respond to test requirements of new generation
devices; high accuracy, dealing with increasing number
of pins and improvement in assembly and wiring quality.
A high-density mounting technology was developed to meet
these demands. A new high accuracy coaxial connector,
integrated into the socket board area, enables short
delivery times, reduction of Hifix costs and design
resources.
Reduced Execution Time of High
Accuracy Calibration
High accuracy calibration
at the device is a requirement, and existing timing
calibration techniques have execution time and expense
penalties. The T5593 implements a new calibration
technique reducing the number of fixtures required for
calibration execution, shortening acquisition time
(which is ten times faster than our conventional model),
and a reduction of the number of acquisition conditions
necessary. These new features both shorten TAT and
improve production
utilization. | |
|
|
|
| |
T5593 |
| Target
Devices: |
DDR2 SDRAM,
High-speed SRAM |
| Simultaneous Testing: |
Up to 128
devices / system |
| Test
Speed: |
533MHz/1.066GHz(DDR
mode) | |
|
|
|
